1. Field of the Invention
The present invention relates to a slot control method of a multi-port network switch and a switch structure therefor. More particularly, the present invention relates to a slot control method of a shared memory structure with a fixed sequence and a dynamic slot effect.
2. Description of the Prior Art
Recently, Internet has become wildly popular due to fast communication, exemption of limitation in time or space, and capability of processing a lot of data. Accordingly, various network protocols and commercialized products are developed. Ethernet is promising since it is low in cost, simple in assembly, easy in management and convenient for training. Therefore, a multi-port Ethernet switch for connecting a plurality of Ethernet architectures is significant.
As shown in FIG. 1, a conventional multi-port Ethernet switch 10 is a network switch of a distributed structure in which a switch fabric 19 for transmitting data packets is connected to a plurality of transportation ports 11,13 and 15. Each of the transportation ports 11, 13 and 15 is coupled to an input packet buffer 117 for receiving data packets from a network interface and transmitting the data packets to the switch fabric 19, an output packet buffer 113 for receiving data packets from the switch fabric 19 and transmitting the data packets to a network interface, and a routing table 115 for registering other address data. Since such a distributed network switch 10 has to be provided with at least three independent memory ICs, it is difficult in manufacture and high in cost, although a considerable bandwidth is provided.
In view of the above shortcomings of the distributed multi-port network switch, as shown in FIG. 2, another multi-port network switch 20 having a shared memory structure is proposed. In such a structure, the packet buffers 113 and 117 and the routing table 115 mentioned above are integrated in a shared memory 29 as a packet buffer 293 and a routing table 295, both of which can be shared among multiple ports, so that the occupied space and the memory capacity needed are decreased, thereby reducing the manufacture cost. Each of the transportation port 21, 23 an 25 is divided into RX DMA 211, RX FIFO 215 and RX MAC 213 for performing data packet transmission to the shared memory 29, and corresponding TX DMA 217, TX FIFO 219 and TX MAC 218 for retrieving data packets from the shared memory 29. In addition, if the shared memory 29 consists of a DRAM of a larger memory capacity, since the DRAM uses capacitors to store data, signal for refreshing data stored in the routing table 295 and the shared memory 29 should be supplied in the network switch 20 by function block memory refresh 28. The other, function blocks such as routing table ageing 24 is use for routing table maintain, CPU interface control 26 is for CPU access switch registers and shared memory 29.
Only one memory (i.e., the shared memory 29) is used in the multi-port network switch of the shared memory structure to serve a plurality of transportation ports and function blocks, and thus how to coordinate the transportation ports and the function blocks with a limited bandwidth is very important. Therefore, a slot controller 27 and a memory interface control 279 are provided in the multi-port network switch having the shared memory to control operations of the transportation ports or the function blocks.
Arbitration is one of the transmission sequence control methods adopted by the slot controller 2. As shown in FIG. 2, when one of the transportation ports sends a transmission request signal, the request may be allowed only after other transmission operations which have been allowed are completed. Accordingly, almost every transportation port or function block has to wait a longer time, resulting in packet latency and data underrun or data overflow. Also, many internal FIFOs are needed and the whole transmission period cannot be handled. Further, the possibility of allowing transmission for each of the transportation ports is not equal.
To improve the disadvantageous slot control method using arbitration, a round-robin processor 275 is additionally provided. As shown in FIGS. 2 and 2A, priority for the last-allowed function block or transportation port is lowest to maintain transmission equality in the network. However, such a way cannot effectively solve the problems of difficulty in handling the whole period, requirement of many internal FIFOs and packet latency.
To this end, another slot control method for use in a multi-port network switch of a shared memory structure is proposed. Concepts of a fixed slot sequence and a fixed slot time are introduced so that transportation ports sequentially operate and each of the allowed operations corresponds to a respective slot time. When the current slot time expires, the next transportation port or function block operates immediately. Although the slot control method can achieve network equality and handle the execution period, it still suffers from the following problem. Since the transportation ports each has a respective fixed slot time, if a specified transportation port or function block does not send a request signal, or only few data are transmitted and a slot time is not fully utilized, the network switch still has to wait until the slot time expires. Therefore, many slot times are wasted so that the phenomenon of packet latency cannot be effectively overcome and the necessary number of the internal FIFOs cannot be decreased.
Therefore, it is desired to propose a method to maintain network equality with a fixed sequence while randomly detect the slot operation to effectively decrease the packet latency or decrease internal FIFOs to be used in order to reduce the cost. Even in the case of using DRAMs, a data bus for SRAMs can achieve fill line speed and be efficiently utilized.